AT24C 02, 04, 08, 16, 32, and 64 Cards
AT24C02
Features
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• Internally Organized 256 x 8 (2K)
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 100 kHz (1.8V) and 400 kHz (2.7V, 5V) Compatibility
• Write Protect Pin for Hardware Data Protection
• 8-byte Page (2K) Write Modes
• Partial Page Writes Allowed
• Self-timed Write Cycle (5 ms max)
• High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Devices Available
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2×3), 5-lead SOT23, 8-lead TSSOP and 8-ball dBGA2 Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
The AT24C02 provides 2048 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 256 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT24C02 is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2×3), 5-lead SOT23 (AT24C02), 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
Operating Temperature…………………………….–55°C to +125°C
Storage Temperature ……………………………….–65°C to +150°C
with Respect to Ground ……………………………… –1.0V to +7.0V
Maximum Operating Voltage …………………………………… 6.25V
DC Output Current……………………………………………….. 5.0 mA
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.
The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or opencollector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C02. As many as eight 2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).
Table 2: Write Project
| WP Pin Status |
Part of the Array Protected |
| At VCC | Full (2K) Array |
| At GND | Normal Read/Write Operations |
AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing.
Device Operation
The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below.
A high-to-low transition of SDA with SCL high is a start condition which must precede any other command.
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode.
Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
The 2K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation.
The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM.
These 3 bits must compare to their corresponding hard-wired input pins.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state.
After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
Write Operations
The 2K EEPROM is capable of an 8-byte page write,.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2K) . The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition. The data word address lower three (2K) are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (2K) data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten.
A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition.At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete.
The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition.
A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition.The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition.
Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue.The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition.
AT24C01 is one kind of Atmel Series Cards that is a kind of contact IC memory card without encryption process.
A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition.The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition.
AT24C Series Card
AT24C Series Card includes a series of chips:
AT24C01, AT24C02, AT24C04, AT24C16, AT24C32,AT24C64,AT24C128,AT24C256,AT24C512,AT24C1024.
This AT24C** device is optimized for use in many industrial and commercial applications.
AT24C01 is original from Atmel.
About the IC module:
AT24C01 provides 1-K bits EEPROM, organized as 128 words of 8 bits each.(128 x 8 )
AT24C02 provides 2-Wire serial EEPROM 2K bits.
AT24C04 provides 2-wire serial EEPROM 4K bits.
AT24C16 provides 2-wire serial EEPROM 16K bits.
AT24C64 provides 2-wire serial EEPROM 64K bits.
AT24C128 provides 2-wire serial EEPROM 128K bits.
AT24C256 provides 2-wire serial EEPROM 256K bits.
AT24C512 provides 2-wire serial EEPROM 512K bits.
AT24C1024 provides 2-wire serial EEPROM 1024K bits.
-EEPROM Endurance minimum 100, 000 erase / write cycles
-Minimum of 10 years data storage time
-Contact confguration and serial interface in accordance to ISO standard 7816
